In general, amorphous silicon (a-Si) has disadvantages such as low mobility of an electron which is a charge carrier, a lower aperture ratio, disharmony with a CMOS process, and so on. On the other hand, a polysilicon thin film transistor allows a drive circuit required for entry of an image signal into a pixel to be formed on a substrate together with a pixel TFT array, which has been impossible in an amorphous silicon TFT. Therefore, since the polysilicon TFT requires no connection between a plurality of terminals and a driver IC, it is possible to increase productivity and reliability and reduce the thickness of a panel. In addition, since a polysilicon TFT process can use fine forming technology of a silicon LSI as it is, it is possible to form a fine structure in an interconnection, and so on. As a result, since there is no limitation in pitch for TAB mounting of the driver IC in the amorphous silicon TFT, it is possible to readily reduce the pixel size and form a plurality of pixels in a small angle of view. In comparison with the TFT using amorphous silicon, the TFT using polysilicon in an active layer has high switching performance and a channel position of the active layer is determined through self alignment to enable fabrication of a compact device and CMOS. Therefore, the polysilicon TFT has been used as a pixel switch device of an active matrix flat panel display (for example, a liquid crystal display, an organic light emitting diode display device, and so on) to realize a chip on glass (COG) product in which a screen size is increased and a driver is installed.
The inventors have filed Korean Patent Application No. 2004-37952, which discloses a method of crystallizing an amorphous silicon layer into a polysilicon layer. According to the method, a conductive layer is formed on the amorphous silicon layer, and an electric field is applied to the conductive layer to induce Joule heating to thereby generate a high temperature heat. As a result, better crystallization, activation of dopant, a thermal oxidation process, and recovering of crystal lattice defects can be performed at a lower temperature, preferably a normal temperature within a shorter time than the conventional art. In addition, it is possible to prevent damage to the substrate due to the high temperature. However, when the method is applied to an actual process of fabricating a polysilicon TFT, a separate conductive layer must be formed.
Meanwhile, when a wire used in the TFT is used as the conductive layer for inducing Joule heating in order to solve the problems without forming the separate conductive layer, the following problems may occur.
FIG. 1 is a plan view of a conventional TFT used in a flat panel display.
Referring to FIG. 1, a straight gate line 100 is disposed in one direction. A gate electrode 101 is disposed to be connected to the gate line 100 in a vertical direction. A semiconductor layer 102 crossing the gate electrode 101 is disposed not to overlap the gate line 100. In addition, source and drain electrodes 103a and 103b are disposed to be connected to source and drain regions of the semiconductor layer 102.
In the conventional TFT structure, when an electric field is applied to the gate line 100 to crystallize an amorphous silicon layer into a polysilicon layer by Joule heating, a sufficient amount heat cannot be transmitted to the gate electrode 101 such that the amorphous silicon layer disposed on a region crossing the gate electrode 101 cannot receive the sufficient amount of heat required for crystallization. As a result, even when the amorphous silicon layer, which is to be used as a semiconductor layer of the TFT, is not crystallized into the polysilicon layer or partially crystallized, crystallization of the polysilicon layer may be uneven to decrease characteristics of the TFT.